SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

Digital Logic RTL & Verilog Interview Questions

Formal Verification: An Essential Toolkit for Modern VLSI Design

Logic Design and Verification Using SystemVerilog (Revised)

A Practical Guide to Adopting the Universal Verification Methodology (Uvm) Second Edition

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

Getting Started with UVM: A Beginner's Guide

Advanced UVM